The present invention relates to a technique for testability of a semiconductor integrated circuit.
FIG. 12 shows a configuration for the conventional method of testing a semiconductor integrated circuit. In FIG. 12, reference numeral 0201 designates a chip, numeral 0202 an internal memory (RAM: random access memory), numeral 0203 a CPU (central processing unit), numeral 0204 a circuit to be tested, numeral 0205 internal buses for connecting the aforementioned component parts to each other, numeral 0206 a scan test circuit connected to the internal buses 0205 and the circuit to be tested 0204, numeral 0206a signal lines for connecting the scan-test related terminals of the circuit to be tested 0204 to the scan test circuit 0206, and numeral 0207 an external bus IF (interface) unit for connecting the internal buses 0205 to input-output terminals 0208.
When testing the circuit under test 0204, the scan test circuit 0206 is controlled through the buses 0205 from the CPU 0203 or the input-output terminals 0208. The test data are set and input to the scan-test related terminals of the circuit to be tested 0204. Then, the value of the scan-test related terminals of the circuit to be tested 0204 is read out.
This method of testing the integrated circuit is called a full scan test method. The method is based on the following facts. All the registers in the circuit to be tested 0204 are replaced by scan registers and connected in a scan chain. As a result, the registers that can be controlled or observed directly from the buses are also replaced by scan registers. The scan register, however, occupies a larger area than the ordinary register. As a result, a large chip size is required to replace all the registers with scan registers.
Also, at the time of the scan test, a scan clock for the scan test is input to the circuit to be tested 0204 from the scan test circuit 0206 in addition to the clock for normal operation. The test clock is generated and output by controlling the scan test circuit 0206 through the buses 0205 from the CPU 0203 or the input-output terminals 0208. Normally, however, the bus speed is lower than the speed of the internal clock. Therefore, the test cannot be conducted at the same speed as the normal operation.